Principal AMS Verification Engineer (m/f/d)

Job description

As Senior / Principal Verification Engineer, you will: Work with the global design teams to do complex SOC verification for digital/analog/FW design Be responsible for verification plan quality, verification result/design target cross-check, test case development to reach better coverage and verification quality Co-work with functional verification team to ensure the complex SoC verification functional coverage and quality We are looking for: 5+ years hands-on experience in Chip-Level AMS Verification on medium-complex designs, for example Transceivers Systems having: variable boot-up sequences; diverse operation-modi; diverse supply domains; diverse communication protocols In this context, it is required specific knowledge about: writing an exhaustive Top-Level AMS verification plan; setting-up an AMS flow, harmonizing it to the Digital Verification flow; techniques for minimizing simulation time and maximizing coverage Knowledge of the Analog and Digital Design Flows, with hands-on experience on at least one of the two Knowledge of the Cadence AMS suite Scripting/Language skills (in bold the required ones): C/C++, Bash, Python, Verilog / VerilogAMS, System-Verilog, Tcl, WREAL Abi...