ASIC Formal Verification Engineer, TPU Compute

Job description

Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience in silicon development or ASIC/SoC design. - Experience with SystemVerilog Assertions (SVA), and formal verification methods. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. - 10 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips. - Experience with one or more formal verification platforms (e.g., Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal). - Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking. - Experience in formally proving correctness of arithmetic units such as floating point adders and multipliers. - Experience working with schedulers, NOCs and networking topologies, protocols (AXI/AMBA). About the job: In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will...