Analog / Mixed-Signal PLL Design Engineer, Senior - Cork, Ireland

Job description

Company: QT Technologies Ireland Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: About the role Qualcomm’s Mixed-Signal IP high-speed clocking and Phased Locked Loop (PLL) design team is seeking Analog / Mixed-Signal design engineers to join our team in Cork, Ireland. The successful candidate will work on analog and mixed-signal integrated circuits for high-speed clocking IP for SoC and PHY level integration into Qualcomm's Mobile, Auto, IoT & Compute SoC products. The primary focus of the work is on low-power and low-voltage mixed-signal design with emphasis on advanced nanometer FinFET & Gate-All-Around (GAA) technology nodes. The successful candidate will both design key circuit blocks and work closely with layout engineers to ensure the layout is fully optimized and complies with best analog layout practices. You will be directly involved in delivering next-generation PLL designs for Qualcomm SoCs and will be part of a large analog mixed-signal design team involved in architecture analysis and IP delivery in leading-edge process technology nodes at 3nm and beyond. The role requires industry experience in transistor-level circuit imple...