Senior Packaging Design Engineer, Silicon

Job description

Minimum qualifications: - Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience. - 5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition with package tape-outs. - Experience in chip package substrate layout, design rules/verification, design for manufacturing (DFM) and taping out for production. - Experience in mobile SOC package design in the following technologies: FCCSP, Package on Package (PoP), InFO, RDL, IPD, 2.5D/3D, Chiplet. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. - Experience in package outline, package routing strategy, bump and ball grid array (BGA) assignment, netlist management. - Experience in package design intercept of new packaging technologies and new silicon interfaces/subsystems. - Experience in physical verification flow development (e.g., Layout Versus Schematic (LVS), Design Rule Checking (DRC), connectivity). - Experience with CAD for creating simple mechanical drawings, such as Package...