Senior Testchip SoC Physical Design Engineer (Integration & Methodology)
Intel · Hillsboro, Oregon, US
Job Description: About the Role Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration t...
Job description
Job Details: Job Description: About the Role Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness. In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes. What You’ll Do: Key responsibilities will include but not limited to: - Developing layout design methodology for testchip development in next generation process nodes - Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips. - Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration - Building and executing tactical plans to conve...