Senior Analog Engineering Manager

Job description

Company Description We are seeking a Senior Analog Engineering Manager to lead the development of DDR5 and next-generation DDR6 PHY solutions for advanced SoCs. This role requires deep technical expertise in high-speed memory interfaces, combined with strong people leadership and program ownership. The successful candidate will manage a team responsible for end-to-end delivery of high-performance, low-power DDR PHYs, from architecture through silicon bring-up, while shaping the roadmap for DDR6-class signaling and architecture Job Description: Technical Leadership (DDR5 / DDR6): - Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures. - Provide technical oversight for critical analog and mixed-signal blocks, including: - High-speed TX/RX datapaths - Advanced equalization, termination, and training circuits - DLL/PLL-based clocking solutions for multi-GHz operation - Voltage, reference generation, and power-aware IO design - Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates. - Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and...