SoC Silicon Top-Level Floorplan Engineer

Job description

Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 10 years of experience in physical design (e.g., with a focus on floorplanning, integration, or top-level chip assembly). - Experience in 3D Integrated Circuit (3D IC) design (e.g., multi-die partitioning, TSV planning, advanced chiplet and packaging technologies, optimizing PPA, and physical verification in a SiP context). - Experience in physical design working on advanced nodes. - Experience collaborating with cross-functional teams (e.g., architecture, RTL design, synthesis, verification). Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture. - Experience in scripting languages (e.g., Python, Tcl, or Perl) and industry standard tools including Innovus, FusionCompiler. - Experience working on various technologies (e.g., embedded processors, DDR, SerDes, HBM, networking-on-chip fabrics, etc.). - Experience using EDA tools to resolve DRC/LVS/EMIR issues for leading edge nodes. - Experience with SoC design me...