Silicon Design Verification Engineer, Quantum AI

Job description

Minimum qualifications: - Bachelor's degree in Electrical Engineering or a related technical field, or equivalent practical experience. - 4 years of experience in silicon design verification using SystemVerilog/UVM. - Experience with SOC verification including CPUs, bus interfaces, or peripherals. - Experience in scripting languages such as Python or Perl, for automation and analysis. Preferred qualifications: - Master's degree or PhD in Electrical Engineering or Computer Science. - 2 years of experience with design verification. - Experience in ARM, RISC-V or any processor based DV including tool chains and C based testing, and with the full digital design verification cycle from spec through bring-up. - Experience with industry standard protocols, interfaces, and IP components, such as PCIe, Ethernet, and NoCs. - Experience running DV for mixed-signal ASICs containing analog and RF IP and building mixed-mode models for end-to-end DV coverage. - Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV. About the job: Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of G...