Senior Analog Layout Engineer

Job description

High Performance Analog (HPA) PL is looking for a Senior Layout Design Engineer who will be responsible for chip and block level layout of high-performance analog and mixed-signal products. A successful candidate will operate as the lead layout design engineer for the PL. The candidate will set up and debug LVS, DRC, ERC environments for the project team, as well as collaborate with lead chip design engineer on chip-level floor-plan. In addition, the candidate will layout critical building blocks such as high-resolution (e.g. 24-bit) analog-to-digital converters, precision voltage references, and HV chopper-stabilized amplifiers. As the lead layout design engineer of the PL, the candidate will also mentor fellow layout design engineers on techniques and best practices for high-precision and low-noise analog designs. As a key member of the team, you will be responsible for: · Driving/delivering floorplan activities at both IPs and/or SOC level. · Participating to the power supply strategy, signals distribution between blocks. · Delivering Analog layout blocks and/or top floorplan strategy. · Driving the top-level integration using the Mixed Signal on Top flow. · Leading a layout tea...