TPU PCIe RTL Design Engineer

Job description

Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 5 years of experience in ASIC design, including one project focused on PCIe logic. - Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl. - Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition. - Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM. - Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows. Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. - 8 years of ASIC design experience, including 3 years in PCIe (Gen4/5/6) controller or protocol logic. - Experience with advanced RTL design, including multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning. - Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up. - Experience in PCIe architecture, including L...