PD - Sr Staff - Physical Verification Lead | Signoff & DRC

Job description

ABOUT THE ROLE: As a Sr Staff / Principal Physical Verification Engineer , you will be the technical owner of all signoff physical verification activities across advanced process nodes. You will lead DRC, LVS, and DFM sign-off at chip top level, drive hierarchical verification strategies, and own bump planning and package-level DRC across Intel, TSMC, Samsung, and GlobalFoundries technologies spanning 28nm through 2nm. You will be a partner with physical design, package engineering, and foundry teams to ensure first-pass tape out success on chiplet-based products. KEY RESPONSIBILITIES: Signoff Physical Verification — Top Level - Own end-to-end physical verification signoff strategy from block level through chip top, ensuring all DRC, LVS, ERC, and antenna violations are cleanly resolved before tapeout. - Define and execute hierarchical DRC methodology across multiple abstraction levels (block, partition, top), leveraging Calibre or IC Validator in hierarchical and distributed modes. - Drive full-chip DRC convergence across advanced nodes including 28nm, 22nm, 14nm, 7nm, 5nm, 3nm, and 2nm at Intel, TSMC, Samsung, and GlobalFoundries. - Develop waiver management processes with foundr...