Senior ASIC DV Engineer

Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Using your thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design engineers to verify fixes. Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. Replicating silicon bugs in simulation environments and validating fixes or SW workarounds. Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up. Evaluating latest verification methodologies and dev...