FPGA Digital Design and Verification Engineer-Contract

Job description

Job Details: Job Description: Altera is seeking a highly motivated FPGA Digital Design and Verification Engineer-Contract. This 6 month ACE contract provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for candidates eager to grow their expertise in RISC-V design, SystemVerilog, UVM-based verification, and digital design methodologies. You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products. Key Responsibilities: RISC-V design: Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems Create self-checking testbenches, constrained-random tests, and functional coverage models Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim) Assist in debugging RTL and verification failures, working closely with design engineers Verify common communication protocols (e.g., UART, SPI) and custom interconnects Contribute to documentation of...