Senior DFT Engineer (Einfochips)

Job description

Position: Senior DFT Engineer (Einfochips) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress: ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS: Mismatch debug using Verdi: Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For: 5 – 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification: Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Too...